This topic covers the fundamental architecture and internal operations of the Central Processing Unit (CPU). It examines the roles of specific registers, the function of the Arithmetic and Logic Unit (ALU) and Control Unit, and the mechanics of the Fetch-Decode-Execute cycle, including how these relate to assembly language and processor performance.
The structure and function of the processor is a foundational topic in computer science that explores how the central processing unit (CPU) executes instructions. The processor is the brain of the computer, responsible for fetching, decoding, and executing instructions stored in memory. Understanding its internal components—such as the control unit (CU), arithmetic logic unit (ALU), registers, and buses—is essential for grasping how software controls hardware. This topic also covers the fetch-execute cycle, pipelining, and the role of the program counter (PC), memory address register (MAR), memory data register (MDR), and accumulator (ACC).
In the OCR A-Level specification, this topic appears in Component 1 (Computer Systems) and is assessed through both multiple-choice and extended-response questions. Mastery of the processor's architecture enables students to analyse performance factors like clock speed, cache size, and core count. It also provides a foundation for understanding more advanced concepts such as parallel processing, RISC vs. CISC architectures, and the impact of the Harvard and von Neumann architectures. Without a solid grasp of the processor's inner workings, students will struggle with later topics like assembly language programming and memory management.
This topic is not just about memorising component names; it requires understanding how data flows between components during instruction execution. For example, the fetch-execute cycle involves the PC sending an address to the MAR, the CU initiating a read from memory to the MDR, and then the instruction being decoded and executed by the ALU or CU. Students should be able to trace this cycle step-by-step and explain how pipelining improves throughput by overlapping fetch, decode, and execute stages. Real-world relevance includes understanding why a 3.0 GHz quad-core processor outperforms a 3.0 GHz single-core processor for multitasking.
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