Fundamentals of computer organisation and architecture — AQA A-Level Computer Science

The fundamentals of computer organisation and architecture form the backbone of understanding how a computer system operates at the hardware level. This topic covers the internal structure of a computer, including the central processing unit (CPU), memory hierarchy, and input/output mechanisms. You will explore how data is represented, stored, and processed, and how the fetch-execute cycle drives program execution. Understanding these concepts is crucial for appreciating how software interacts with hardware and for optimising performance.

In the AQA A-Level Computer Science specification, this topic is essential for building a foundation in systems architecture. It links directly to topics such as assembly language, operating systems, and performance analysis. By mastering this area, you will be able to explain how factors like clock speed, cache size, and core count affect processing speed, and how different architectures (e.g., von Neumann vs. Harvard) influence system design. This knowledge is not only exam-relevant but also vital for careers in hardware engineering, embedded systems, and low-level programming.

This topic also introduces key concepts like the stored program concept, where both instructions and data are held in memory, and the role of buses in data transfer. You will learn about the control unit, arithmetic logic unit (ALU), and registers such as the program counter (PC), memory address register (MAR), and memory data register (MDR). These components work together to execute instructions, and understanding their interplay is critical for answering exam questions on CPU performance and pipelining.

• →The von Neumann architecture: a single shared memory for data and instructions, with a single bus for data transfer, leading to the von Neumann bottleneck.
• →The fetch-execute cycle: the process by which the CPU retrieves an instruction from memory (fetch), decodes it, and executes it, using registers like PC, MAR, MDR, and CIR.
• →CPU components: the control unit (CU) coordinates operations, the arithmetic logic unit (ALU) performs calculations, and registers provide fast temporary storage.
• →Memory hierarchy: registers, cache (L1, L2, L3), RAM, and secondary storage, each with different speeds and costs, affecting overall system performance.
• →Pipelining: a technique where multiple instructions are overlapped in execution, improving throughput but introducing hazards (structural, data, control).

• Distinction between von Neumann and Harvard architectures
• Description of the stored program concept
• Role and operation of processor components (ALU, CU, clock, registers)
• Stages of the Fetch-Execute cycle
• Interpretation of processor instruction sets (opcode and operand)
• Application of immediate and direct addressing modes
• Explanation of factors affecting processor performance (cores, cache, clock speed, word length, bus widths)
• Principles of operation for input, output, and secondary storage devices

• 💡Ensure you can clearly distinguish between the roles of the address, data, and control buses.
• 💡Practice tracing the Fetch-Execute cycle with specific register names.
• 💡Be prepared to interpret simple machine code instructions given an opcode/operand format.
• 💡Understand the trade-offs between different secondary storage devices regarding speed, capacity, and cost.
• 💡Use clear, technical terminology when describing processor components.
• 💡When describing the fetch-execute cycle, always name the registers involved (PC, MAR, MDR, CIR) and explain the role of each. For example, during fetch, the PC is copied to the MAR, then the MDR receives the instruction from memory, and it is placed in the CIR for decoding.
• 💡For performance questions, use comparative language: 'A larger cache reduces the average memory access time because it stores frequently used data closer to the CPU.' Avoid vague statements like 'it makes it faster.'
• 💡In questions about pipelining, clearly state that it increases throughput (instructions per second) but does not reduce the latency of a single instruction. Also, mention hazards and how they can be mitigated (e.g., branch prediction).

• Confusing the roles of the address bus and data bus
• Failing to explain the difference between von Neumann and Harvard architectures correctly
• Misinterpreting the Fetch-Execute cycle stages
• Incorrectly applying addressing modes
• Confusing the purpose of different secondary storage devices
• Misconception: The clock speed alone determines CPU performance. Correction: While clock speed is important, factors like cache size, number of cores, and pipelining also significantly impact performance. A CPU with a lower clock speed but larger cache and more cores can outperform a higher-clocked CPU.
• Misconception: RAM is the same as secondary storage. Correction: RAM is volatile memory used for temporary data storage during program execution, while secondary storage (e.g., hard drives, SSDs) is non-volatile and used for long-term data storage. They serve different purposes in the memory hierarchy.
• Misconception: The fetch-execute cycle only runs once per instruction. Correction: The cycle repeats continuously for each instruction in a program. The program counter is updated to point to the next instruction, and the cycle loops until the program ends or is interrupted.