Fundamentals of computer organisation and architecture — AQA A-Level Computer Science
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Fundamentals of computer organisation and architecture explained
Addressing modes define how instructions specify the location of operands, a fundamental aspect of computer architecture that directly impacts assembly language programming and compiler design.
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Understanding these modes is essential for analysing instruction sets, optimising memory access, and writing efficient low-level code.
Your focus
- Describe the role of addressing modes in the fetch-decode-execute cycle
- Differentiate between immediate, direct, indirect, indexed, and relative addressing modes using assembly language examples
- Evaluate the suitability of each addressing mode for different programming tasks such as accessing array elements, constants, and dynamically allocated memory
Show all 5 objectives
- Apply addressing mode concepts to calculate effective addresses and predict memory accesses
- Analyse the impact of addressing mode choice on code size and execution speed
Fundamentals of computer organisation and architecture exam tips
Topic Overview
Fundamentals of computer organisation and architecture explores the internal structure and operation of a computer system. It covers the components that make up a CPU, how they interact to execute instructions, and the principles of memory hierarchy and I/O systems. Understanding this topic is essential for grasping how software controls hardware and how performance can be optimised.
This topic forms the backbone of computer science, linking low-level hardware design to high-level programming. It explains the fetch-execute cycle, the role of registers like the PC and MAR, and the difference between Von Neumann and Harvard architectures. Mastery of these concepts is crucial for topics such as operating systems, assembly language, and performance analysis.
In the AQA A-Level specification, this topic appears in Paper 1 and Paper 2, often in questions about CPU components, pipelining, and memory. A solid understanding here supports later study of processor scheduling, cache memory, and parallel systems. It also provides the vocabulary needed to discuss computer performance in exams and beyond.
Key Concepts
- →Von Neumann architecture: a single shared memory for data and instructions, with a single bus for data transfer between CPU and memory.
- →The fetch-execute cycle: the process by which the CPU retrieves an instruction from memory (fetch), decodes it, and carries it out (execute).
- →CPU registers: PC (Program Counter), MAR (Memory Address Register), MDR (Memory Data Register), ACC (Accumulator), and CIR (Current Instruction Register) – each with a specific role.
- →Pipelining: a technique that allows the CPU to fetch the next instruction while executing the current one, improving throughput.
Marking Points
- Award credit for correctly identifying the operand location for each addressing mode in a given instruction
- Expect accurate conversion of a high-level array access (e.g., A[i]) to indexed addressing with base and offset
- Look for explicit reference to the role of registers (e.g., index register, base register) where applicable
- In longer responses, reward demonstration of how relative addressing supports relocatable code and reduces link-time work
Examiner Tips
- 💡When given an assembly snippet, always write down the effective address calculation step by step for each instruction
- 💡For compare-type questions, use concrete code examples to illustrate differences, e.g., loading a constant vs. accessing a table
- 💡Link each addressing mode to a high-level language construct: immediate for constants, indexed for arrays, indirect for pointers, relative for labels
- 💡In multiple-choice questions, rule out modes that involve memory if the instruction clearly has a register operand
- 💡Always label registers with their full names (e.g., Program Counter, not just PC) in the first use to show understanding. In diagrams, clearly show the direction of data flow on buses.
- 💡When explaining the fetch-execute cycle, use a step-by-step approach: mention the role of each register at each stage. For example, 'The PC sends the address to the MAR via the address bus, then the MDR receives the instruction from memory via the data bus.'
- 💡For performance questions, remember that clock speed, number of cores, and cache size all affect performance. Be specific: 'A larger cache reduces the average memory access time, improving CPU performance.'
Common Mistakes
- Confusing direct and indirect addressing—direct provides a memory address, indirect provides an address that holds the actual address
- Misinterpreting relative addresses as absolute offsets, leading to incorrect effective address calculation when the program counter is involved
- Overlooking the limited range of immediate values and assuming they can hold any constant
- Incorrectly summing base and index registers in indexed addressing, especially when scaling is involved
- Misconception: The PC holds the current instruction being executed. Correction: The PC holds the memory address of the next instruction to be fetched; the CIR holds the current instruction.
- Misconception: Harvard architecture uses separate buses for data and instructions, but Von Neumann uses a single bus. Correction: Both architectures use buses; the key difference is that Harvard has physically separate memory and buses for data and instructions, while Von Neumann shares a single memory and bus.
- Misconception: Pipelining always speeds up execution. Correction: Pipelining can cause hazards (e.g., data dependencies) that may stall the pipeline, reducing the speedup.
Frequently Asked Questions
What is the difference between Von Neumann and Harvard architecture?
Von Neumann architecture uses a single memory space for both data and instructions, connected to the CPU via a single bus. This can create a bottleneck (the Von Neumann bottleneck) because the CPU cannot fetch data and instructions simultaneously. Harvard architecture has separate memory and buses for data and instructions, allowing simultaneous access, which can improve performance. Modern CPUs often use a modified Harvard architecture with separate caches but shared main memory.
How does the fetch-execute cycle work step by step?
The cycle has three stages: fetch, decode, and execute. In fetch, the PC sends the address of the next instruction to the MAR, which places it on the address bus. The instruction is then read from memory into the MDR via the data bus, and copied to the CIR. In decode, the control unit interprets the instruction in the CIR. In execute, the ALU performs the required operation (e.g., addition, load, store). The PC is then incremented to point to the next instruction, and the cycle repeats.
What are the main CPU registers and what do they do?
Key registers include: Program Counter (PC) – holds the address of the next instruction; Memory Address Register (MAR) – holds the address of memory location to be accessed; Memory Data Register (MDR) – holds data read from or written to memory; Accumulator (ACC) – stores intermediate results of ALU operations; Current Instruction Register (CIR) – holds the current instruction being executed. Each plays a specific role in the fetch-execute cycle.
How does cache memory improve CPU performance?
Cache memory is a small, fast memory located close to the CPU that stores frequently used data and instructions. When the CPU needs data, it first checks the cache. If the data is there (a cache hit), it can be accessed much faster than from main memory (RAM). This reduces the average memory access time, as the CPU spends less time waiting for data. Multiple levels of cache (L1, L2, L3) balance speed and size.
What is pipelining and how does it work?
Pipelining is a technique where the CPU overlaps the fetch, decode, and execute stages of multiple instructions. For example, while one instruction is being executed, the next is being decoded, and the one after that is being fetched. This increases throughput (instructions per clock cycle). However, hazards like data dependencies (e.g., an instruction needs the result of a previous one) can cause stalls, reducing efficiency.
What is the Von Neumann bottleneck?
The Von Neumann bottleneck refers to the limitation on throughput caused by the single shared bus between the CPU and memory in Von Neumann architecture. Since both data and instructions travel over the same bus, the CPU can only fetch one at a time, limiting performance. This is why modern systems use caches and separate buses to mitigate the bottleneck.