Boolean logic: Create the Boolean expression for a simple logic circuit.

The idea

Here you turn a simple logic circuit diagram into a Boolean expression. Read the circuit from its inputs towards its output. Name each input with a letter, such as A, B and C. Identify each gate: an AND gate joins its inputs with a dot, an OR gate joins them with a plus, and a NOT gate puts a bar over its input or output. Where a gate feeds another gate, bracket that part so the grouping is clear. For example, if A and B enter an AND gate and that output joins C at an OR gate, the expression is (A . B) + C. If a NOT gate inverts A before it reaches the AND gate, write the expression with A negated. A multiple-choice question will offer several expressions and ask which one matches the circuit, so check each gate and each connection in turn.

What earns the marks

• Names each circuit input with a letter and tracks it through the gates to the output.
• Uses the dot for AND gates and the plus for OR gates in the expression.
• Represents a NOT gate by negating the relevant input or sub-expression.
• Brackets a sub-expression where one gate's output feeds into another gate, so the grouping matches the circuit.
• Selects the expression whose structure matches the order and connections of the gates in the diagram.

Common mistakes and how to put them right

• Ignoring the order in which gates are connected and writing inputs in a flat list.

  Put it right: Bracket the output of an earlier gate before it feeds the next.

• Using the wrong symbol for a gate, such as a plus for an AND gate.

  Put it right: Match each gate type to its operator, dot for AND and plus for OR.

• Omitting a NOT gate so an inverted input is written as plain.

  Put it right: Negate that input or sub-expression wherever the NOT gate appears.

Exam tips

• Label every input and every gate output on the diagram before writing the expression.
• Work from the inputs towards the output, writing a bracketed sub-expression at each gate.
• Compare your finished expression against each option, checking gate types and groupings one at a time.