AQA · A-Level · Physics

    Course version: 7408 · Version from Sept 2016

    The astable as an oscillator to provide a clock pulse.

    Full specification wording

    Astables (A-level only): The astable as an oscillator to provide a clock pulse.

    An astable circuit has no stable output state: it continuously switches between two output levels, producing a square wave.

    Checked against the AQA 7408 specification (opens in a new tab) on .

    • Point 1 of 3
    • 4 key terms

    Study notes

    From the checked teaching notes for this specification point.

    The idea

    An astable circuit has no stable output state: it continuously switches between two output levels, producing a square wave. In this specification you treat the astable as an oscillator that supplies a clock pulse to sequential logic. The frequency depends on the resistor and capacitor values in the timing network, so changing R or C changes the clock rate. You should be able to describe the output waveform, explain that it alternates indefinitely without an external trigger, and relate the period to the timing components. You are not required to derive the internal operation of the astable from first principles.

    What earns the marks

    • Describe the astable output as a continuous square wave alternating between two levels.
    • Explain that the astable has no stable state and needs no external trigger to oscillate.
    • Identify the resistor and capacitor in the timing network as the components that set the frequency.
    • Relate a larger time constant to a longer period and therefore a lower clock frequency.
    • Explain the role of the clock pulse in advancing a sequential logic circuit.

    Common mistakes and how to put them right

    • Describing the astable as a bistable or monostable.

      Put it right: State that the astable has no stable state and oscillates continuously.

    • Claiming the output frequency is independent of the timing components.

      Put it right: Link frequency to the resistor and capacitor values.

    • Stating that an external trigger is needed to start each cycle.

      Put it right: Explain that the astable switches automatically.

    Exam tips

    • Sketch the output waveform and mark the period and amplitude clearly.
    • Use the phrase 'no stable state' when defining an astable.
    • When asked about clock rate, refer explicitly to the timing resistor and capacitor.

    Try the lesson

    The start of the Astables (A-level only): The astable as an oscillator to provide a clock pulse. lesson, made from checked teaching notes for this specification point.

    Have a go first

    What is the role of an astable circuit when it is used with a sequential logic system?

    Listen

    An astable circuit has no stable output state: it continuously switches between two output levels, producing a square wave. In this specification you treat the astable as an oscillator that supplies a clock pulse to sequential logic. The frequency depends on the resistor and capacitor values in the timing network, so changing R or C changes the clock rate. You should be able to describe the output waveform, explain that it alternates indefinitely without an external trigger, and relate the period to the timing components. You are not required to derive the internal operation of the astable from first principles. A strong answer earns marks for these points. Describe the astable output as a continuous square wave alternating between two levels. Explain that the astable has no stable state and needs no external trigger to oscillate. Identify the resistor and capacitor in the timing network as the components that set the frequency. Relate a larger time constant to a longer period and therefore a lower clock frequency. A common slip: Describing the astable as a bistable or monostable. Instead, state that the astable has no stable state and oscillates continuously. Exam tip: Sketch the output waveform and mark the period and amplitude clearly.

    See it

    A top-down flowchart. The first node reads 'Astable has no stable state' and points to 'Switches continuously between two output levels', which points to 'Produces a square wave'. That node points to 'Oscillates indefinitely without an external trigger' and also to 'Clock pulse advances a sequential logic circuit'. Separately, a node reading 'Timing resistor and capacitor' points to 'Set the frequency', which points to 'Larger time constant gives longer period', which points to 'Lower clock frequency'.
    It shows how the astable's lack of a stable state produces a continuous square wave whose frequency is set by the timing resistor and capacitor, and how that clock pulse advances a sequential logic circuit.

    Key words

    Say what each word means before you turn the card.

    Oscillation

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    Clock pulses

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    Timing circuits

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    Sequential logic

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    See every definition
    Oscillation
    Continuous switching between two output levels with no stable state and no external trigger needed.
    Clock pulses
    Supplied by the astable as an oscillator to advance a sequential logic circuit.
    Timing circuits
    The resistor and capacitor in the timing network set the frequency, so changing them changes the clock rate.
    Sequential logic
    Circuit advanced by the clock pulse that the astable supplies.

    Label the diagram

    Some boxes have lost their names. Pick the right name for each number.

    The diagram again, with 3 boxes numbered instead of named. A top-down flowchart. The first node reads 'Astable has no stable state' and points to 'Switches continuously between two output levels', which points to 'Produces a square wave'. That node points to 'Oscillates indefinitely without an external trigger' and also to 'Clock pulse advances a sequential logic circuit'. Separately, a node reading 'Timing resistor and capacitor' points to 'Set the frequency', which points to 'Larger time constant gives longer period', which points to 'Lower clock frequency'.
    • 1Box 1

    • 2Box 2

    • 3Box 3

    0 of 3 labelled

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