Astables (A-level only) — AQA A-Level Physics

An astable is a type of oscillator circuit that has no stable output state, continuously switching between high and low voltages to produce a square wave. It is a fundamental building block in electronics, used in timers, pulse generators, and clock circuits. In AQA A-Level Physics, you need to understand the operation of astables built from operational amplifiers or the 555 timer IC, and be able to calculate frequency and mark-space ratio from component values.

This topic brings together earlier concepts such as RC charging and discharging, potential dividers, and comparator action. It is essential for understanding how digital systems generate timing signals and is often examined in the context of practical circuit design. Mastery of astables also prepares you for more advanced topics like bistable and monostable circuits.

• →An astable has two unstable states and oscillates continuously without an external trigger, producing a square wave output.
• →The frequency and mark-space ratio are determined by the RC timing network: for a 555 timer, f = 1.44 / ((R1 + 2R2)C) and mark-space ratio = (R1 + R2)/R2.
• →In an op-amp astable, positive feedback sets two threshold voltages, and the capacitor charges and discharges between them, causing the output to switch between positive and negative saturation.
• →The charging and discharging paths in a 555 astable are different: charging through R1 and R2, discharging through R2 only, which affects the duty cycle.
• →The output waveform is a square wave with rise and fall times determined by the slew rate of the op-amp or the internal transistors of the 555.

• Describe the astable output as a continuous square wave alternating between two levels.
• Explain that the astable has no stable state and needs no external trigger to oscillate.
• Identify the resistor and capacitor in the timing network as the components that set the frequency.
• Relate a larger time constant to a longer period and therefore a lower clock frequency.
• Explain the role of the clock pulse in advancing a sequential logic circuit.
• Defines clock rate or frequency as the number of complete pulses per second, measured in hertz, and links it to period by f = 1/T.
• Defines period as the duration of one complete cycle, measured between corresponding points such as successive rising edges.
• Defines pulse width as the time for which the output remains high during one cycle, distinguishing it from the low time.
• Defines duty cycle as pulse width divided by period, expressed as a fraction or percentage.
• Defines mark-to-space ratio as the ratio of high time to low time, simplifying it to whole numbers where possible.
• Applies the definitions to a waveform or timing diagram, reading times from the horizontal scale and calculating the required quantity.
• States that the running frequency of an astable is determined by the external resistor and capacitor values in the timing network.
• Explains that increasing resistance reduces charging or discharging current, so the capacitor takes longer to reach its threshold voltages.
• Explains that increasing capacitance increases the charge stored for a given voltage change, so the capacitor takes longer to charge or discharge.
• Links the period to the RC time constant, noting that period is approximately proportional to the product RC.
• Predicts the effect on frequency of changing R or C, for example doubling either value approximately halves the frequency.
• Selects or compares component values to achieve a required running frequency in a described astable circuit.

• 💡Sketch the output waveform and mark the period and amplitude clearly.
• 💡Use the phrase 'no stable state' when defining an astable.
• 💡When asked about clock rate, refer explicitly to the timing resistor and capacitor.
• 💡Convert milliseconds or microseconds to seconds before substituting into f = 1/T, then state the unit hertz.
• 💡When reading an oscilloscope trace, identify the timebase setting and count divisions carefully for both the high time and the full period.
• 💡Give duty cycle as a fraction or percentage and mark-to-space ratio in the form high:low, simplifying the ratio where possible.
• 💡Use proportional reasoning: if RC increases by a factor, state the corresponding factor change in period and hence frequency.
• 💡When comparing circuits, identify which component has changed and explain the effect through charging current or stored charge.
• 💡Quote the relationship between period and RC as approximate unless the exact circuit formula is given, and avoid inventing a precise constant.
• 💡Always state the formulas you use and show your working clearly. In calculation questions, marks are awarded for correct substitution and rearrangement, even if the final answer is wrong.
• 💡When describing the operation of an astable, use correct terminology such as 'threshold voltage', 'saturation', 'positive feedback', and 'time constant'. Avoid vague phrases like 'it goes up and down'.
• 💡For 555 astable calculations, remember that the mark-space ratio is always greater than 1 because the charging path includes both resistors while the discharge path includes only R2. If you get a ratio less than 1, you have likely swapped the times.

• Describing the astable as a bistable or monostable; the correction is to state that the astable has no stable state and oscillates continuously.
• Claiming the output frequency is independent of the timing components; the correction is to link frequency to the resistor and capacitor values.
• Stating that an external trigger is needed to start each cycle; the correction is to explain that the astable switches automatically.
• Confusing period with pulse width: the period covers the whole cycle, whereas pulse width covers only the high portion; correct by measuring edge-to-edge for period and high-time only for pulse width.
• Treating frequency and period as directly proportional: they are reciprocals, so doubling the period halves the frequency; correct by using f = 1/T consistently.
• Expressing duty cycle as high time divided by low time: that gives the mark-to-space ratio; correct by dividing pulse width by the full period.
• Believing the supply voltage sets the running frequency: the frequency is set mainly by the external RC network, so correct by focusing on R and C values.
• Assuming frequency is directly proportional to RC: period is approximately proportional to RC, so frequency varies inversely with RC; correct by using the reciprocal relationship.
• Ignoring the effect of changing only one component: changing either R or C alters the timing, so correct by considering the product RC rather than one value alone.
• Students often think the capacitor in a 555 astable charges through R1 only and discharges through R1 and R2. In fact, it charges through R1 and R2 in series and discharges through R2 only.
• Many believe that the frequency of an op-amp astable depends on the supply voltage. While the threshold voltages scale with supply, the time constant and the ratio of thresholds remain constant, so frequency is largely independent of supply voltage.
• Some students confuse astable with monostable, thinking an astable needs a trigger. An astable is free-running and requires no external trigger.

1. 1Day 1-2: Revise the fundamentals of RC circuits and op-amp comparators. Practice calculating time constants and threshold voltages.
2. 2Day 3-4: Learn the 555 timer astable circuit diagram and derive the formulas for t1, t2, T, and f. Memorise the key equations.
3. 3Day 5-6: Study the op-amp astable circuit. Understand how positive feedback sets the thresholds and derive the expression for frequency.
4. 4Day 7-8: Work through past paper questions on astables, focusing on calculations and explanations. Mark your answers using the mark scheme.
5. 5Day 9-10: Create a summary sheet with circuit diagrams, formulas, and key explanations. Test yourself with active recall questions.

• 📋Calculation of frequency and mark-space ratio for a 555 astable given resistor and capacitor values. Advice: write down the formula, substitute carefully, and check units.
• 📋Explanation of the operation of an op-amp astable, including how the capacitor voltage and output voltage vary with time. Advice: describe the charging and discharging phases and reference the threshold voltages.
• 📋Design question: choose component values to achieve a specified frequency or duty cycle. Advice: rearrange the formula and consider practical resistor and capacitor values.
• 📋Comparison of astable, monostable, and bistable circuits. Advice: focus on the number of stable states and the need for a trigger.