AQA · A-Level · Physics
Course version: 7408 · Version from Sept 2016
Sequential logic (A-level only): Outputs from the circuits.
Sequential logic circuits produce outputs that depend on present inputs and stored past states, so reading outputs means tracking how each stage changes over time.
Checked against the AQA 7408 specification (opens in a new tab) on .
- Point 3 of 5
- 4 key terms
Study notes
From the checked teaching notes for this specification point.
The idea
Sequential logic circuits produce outputs that depend on present inputs and stored past states, so reading outputs means tracking how each stage changes over time. In A-level work, you analyse circuits built from logic gates and flip-flops, stating the output of each gate or pin for a given clock sequence. A practical method is drawing a timing diagram: label each clock pulse, mark the state of every flip-flop after each active edge, then evaluate combinational gates. For example, a D-type flip-flop clocked by a square wave passes its D input to Q on each rising edge. Crucially, while flip-flop states update on clock edges, combinational outputs can change asynchronously if external inputs change between pulses.
What earns the marks
- Identify each output node in the circuit and state whether it is taken from a flip-flop (Q or Q̄) or from a combinational gate.
- Track the state of every storage element after each active clock edge before evaluating downstream gates.
- Evaluate combinational gates using the current stored states and any external inputs, applying the correct truth table for each gate.
- Present outputs as a timing diagram or state table with clearly labelled clock pulses and output levels.
- Recognise that while flip-flop states change only at active clock edges, combinational outputs may change asynchronously if external inputs vary between clock pulses.
- Check that unused or asynchronous inputs are held at defined logic levels so outputs are not indeterminate.
Common mistakes and how to put them right
Treating a flip-flop output as changing immediately with its input.
Put it right: Q changes only on the active clock edge.
Evaluating gates before updating the flip-flop states.
Put it right: Update storage elements first, then evaluate combinational logic.
Assuming all circuit outputs are strictly synchronous.
Put it right: Check if combinational gates are connected to external inputs that can change between clock edges.
Leaving unused inputs floating.
Put it right: Tie them to a defined logic level so the output is predictable.
Exam tips
- Draw a timing diagram with one row per signal and align all transitions to clock edges or asynchronous input changes.
- Label each clock pulse number so your sequence is easy to follow and check.
- State the logic level of each output at each step rather than describing it vaguely.
Try the lesson
The start of the Sequential logic (A-level only): Outputs from the circuits. lesson, made from checked teaching notes for this specification point.
Have a go first
A two-bit binary counter is clocked and its outputs are labelled Q₁ and Q₀, where Q₁ is the more significant bit. After the counter has received three clock pulses from its reset state, what are the logic levels of Q₁ and Q₀?
Listen
Sequential logic circuits produce outputs that depend on present inputs and stored past states, so reading outputs means tracking how each stage changes over time. In A-level work, you analyse circuits built from logic gates and flip-flops, stating the output of each gate or pin for a given clock sequence. A practical method is drawing a timing diagram: label each clock pulse, mark the state of every flip-flop after each active edge, then evaluate combinational gates. For example, a D-type flip-flop clocked by a square wave passes its D input to Q on each rising edge. Crucially, while flip-flop states update on clock edges, combinational outputs can change asynchronously if external inputs change between pulses. A strong answer earns marks for these points. Identify each output node in the circuit and state whether it is taken from a flip-flop (Q or Q̄) or from a combinational gate. Track the state of every storage element after each active clock edge before evaluating downstream gates. Evaluate combinational gates using the current stored states and any external inputs, applying the correct truth table for each gate. Present outputs as a timing diagram or state table with clearly labelled clock pulses and output levels. A common slip: Treating a flip-flop output as changing immediately with its input. Instead, Q changes only on the active clock edge. Exam tip: Draw a timing diagram with one row per signal and align all transitions to clock edges or asynchronous input changes.
Key words
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Sequential logic circuits
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Timing diagram
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Clock-edge triggering
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Asynchronous output changes
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See every definition
- Sequential logic circuits
- Circuits that produce outputs depending on present inputs and stored past states, so reading outputs means tracking how each stage changes over time.
- Timing diagram
- A drawing in which each clock pulse is labelled, the state of every flip-flop after each active edge is marked, and combinational gates are then evaluated.
- Clock-edge triggering
- Flip-flop states update on clock edges, so Q changes only on the active clock edge rather than immediately with its input.
- Asynchronous output changes
- Combinational outputs can change asynchronously if external inputs change between pulses, even though flip-flop states update only on clock edges.
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