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    Interrupts — AQA A-Level Computer Science

    An interrupt is a signal sent from a hardware device or software program to the processor, requesting immediate CPU attention and temporarily suspending the current execution sequence. The processor checks for interrupts at the end of each Fetch-Decode-Execute cycle, saving register states to a stack before executing an Interrupt Service Routine (ISR).

    Interrupts explained

    An interrupt is a signal sent to the processor, either by a hardware device such as a keyboard or timer, or by software, asking for attention.

    Read the full explanation

    When an interrupt is raised, the processor finishes the current instruction and then, instead of fetching the next instruction from the normal sequence, it jumps to an interrupt service routine (ISR). An ISR is a short program stored in memory that deals with the event, for example reading a key press into a buffer or updating a clock. Once the ISR finishes, control returns to the interrupted program so that it can continue as if nothing had happened. This changes the Fetch-Execute cycle: after each Execute stage, the processor checks for pending interrupts before the next Fetch. If one is waiting, the cycle is diverted into the ISR.

    Your focus

    1. Describe the role of interrupts and interrupt service routines (ISRs); their effect on the Fetch-Execute cycle; and the need to save the volatile environment while the interrupt is being

    Which command word is this?

    Provide a detailed, chronological account of a process or mechanism without needing extended justification (e.g. describe the stages of handling an interrupt).

    Interrupts exam tips

    Topic Overview

    Interrupts are fundamental control mechanisms within processor architecture that enable efficient communication between the Central Processing Unit, system software, and external hardware devices. Without interrupts, a processor would have to spend significant clock cycles continuously polling input/output devices to check whether they require attention.

    Understanding interrupts is critical for mastering the Fetch-Decode-Execute cycle, operating system resource management, and concurrent task execution. This topic bridges low-level hardware interactions with core operating system functions such as multitasking, memory management, and input/output handling.

    Key Concepts
    • →Polling vs Interrupts: Polling wastes CPU cycles by repeatedly checking peripheral status, whereas interrupts allow the CPU to execute tasks unhindered until alerted.
    • →The Role of the Stack: The stack stores the volatile context (Program Counter and general registers) in Last-In, First-Out (LIFO) order to support nested interrupts.
    • →Interrupt Service Routine (ISR): A specialised mini-program stored in memory designed to handle a specific hardware or software event.
    • →Interrupt Priority: Determines the order of execution when multiple interrupts occur simultaneously or during the execution of an existing ISR.
    Marking Points
    • Defines an interrupt as a signal that asks the processor to stop its current work and attend to an event
    • States that an ISR is a routine that handles a specific interrupt and then returns control
    • Explains that the Fetch-Execute cycle is interrupted after Execute and checks for interrupts before the next Fetch
    • Identifies the volatile environment as register contents such as the program counter and status flags
    • Explains that the volatile environment is saved before the ISR runs so the interrupted program can resume correctly
    Examiner Tips
    • 💡Use the phrase volatile environment and name at least two registers that are saved
    • 💡Describe the order: interrupt raised, current instruction completes, state saved, ISR runs, state restored, program resumes
    • 💡Link each part of your answer to its effect on the Fetch-Execute cycle
    • 💡Always state 'at the end of the Fetch-Decode-Execute cycle' when describing when the CPU inspects the interrupt lines.
    • 💡Explicitly name the 'stack' as the data structure used to store register values and the Program Counter; generic terms like 'saved in RAM' lose marks.
    • 💡When explaining how the CPU locates an ISR, reference the 'Interrupt Vector Table' or vector addresses to show deep architectural understanding.
    Common Mistakes
    • Describes an interrupt as a program that runs on its own; correct it to a signal that causes the processor to switch to an ISR
    • Says the ISR replaces the current program permanently; correct it to say control returns to the interrupted program
    • Places the interrupt check at the start of Fetch; correct it to say the check occurs after the current instruction completes
    • Omits the need to save register contents; correct it to explain that without saving, the program resumes with incorrect values
    • Misconception: Interrupts can halt the execution of an instruction halfway through its cycle. Correction: The CPU always completes the current execute phase; interrupts are checked at the transition boundary between cycles.
    • Misconception: Interrupts only come from external hardware devices like keyboards and printers. Correction: Software interrupts (e.g. division by zero, system calls, page faults) are generated internally by running programs.
    Revision Plan
    1. 1Day 1-2: Master the exact step-by-step sequence of interrupt handling and memorise the register-stack preservation routine.
    2. 2Day 3-4: Compare polling with interrupt-driven I/O and identify software vs hardware interrupt triggers.
    3. 3Day 5: Practice multi-priority scenarios and trace stack states during nested interrupts.
    4. 4Day 6-7: Complete past AQA 4-mark and 6-mark exam questions under timed conditions, cross-checking answers against official mark schemes.
    Exam Question Types
    • 📋Step-by-step sequence questions: Typically 4-6 marks asking students to trace how an interrupt is detected, serviced, and cleared by the CPU.
    • 📋Comparative questions: Asking students to evaluate the differences, advantages, and trade-offs between polling and interrupt-driven processing.
    • 📋Application scenarios: Providing a system context (e.g. a real-time medical monitor or printer buffer) and asking how interrupt priority levels should be configured.
    Command Word Expectations (AQA)
    Describe

    Provide a detailed, chronological account of a process or mechanism without needing extended justification (e.g. describe the stages of handling an interrupt).

    Explain

    Set out the causes, reasons, or mechanisms of why something happens; must include linking phrases like 'which causes' or 'in order to' (e.g. explain why the contents of registers must be saved to the stack).

    Compare

    Identify both similarities and differences between two concepts (e.g. polling versus interrupts), detailing the operational strengths and weaknesses of each.

    How Students Lose Marks (Examiner Pitfalls)
    Pitfall: Stating that the processor immediately stops and handles an interrupt midway through executing an instruction.
    ❌ Weak Answer (Loses Marks):When an interrupt occurs, the CPU stops running the program straight away to run the interrupt code.
    Example improved answer:An interrupt signal is flagged, but the CPU continues and completes the current Fetch-Decode-Execute cycle. The interrupt register is checked specifically at the end of the execute stage prior to fetching the next instruction.
    Examiner Tip: Always specify that the processor completes the current instruction or cycle before checking priority and transferring control to the Interrupt Service Routine (ISR).
    Pitfall: Vaguely mentioning that volatile data is saved to 'memory' without naming the stack or specific CPU registers.
    ❌ Weak Answer (Loses Marks):The computer saves its progress into memory so it can go back to it later.
    Example improved answer:The contents of the Program Counter (PC) and other working registers (such as the Accumulator and Status Register) are pushed onto a system call stack to preserve the state of the interrupted process.
    Examiner Tip: Use precise architectural terminology: explicitly state that register contents, including the Program Counter, are pushed onto the stack and subsequently popped off upon ISR completion.
    Step-by-Step Worked Solutions

    Question: Describe the sequence of events that occurs inside the Central Processing Unit when a higher-priority hardware interrupt signal is detected during the execution of a user program. [6 marks]

    1. 1.Step 1: Identify when the interrupt is detected. State that the CPU finishes the current Fetch-Decode-Execute (FDE) cycle and tests the interrupt register.
    2. 2.Step 2: Compare priorities. Note that because the interrupt is of higher priority than the running process, the CPU accepts it.
    3. 3.Step 3: Save execution context. State that the contents of the Program Counter (PC) and general-purpose registers (e.g. Accumulator, Status Register) are pushed onto the system stack.
    4. 4.Step 4: Load handler address. Explain that the memory address of the relevant Interrupt Service Routine (ISR) is loaded into the Program Counter using an interrupt vector table.
    5. 5.Step 5: Execute ISR. The instructions forming the ISR are fetched, decoded, and executed to service the peripheral or event.
    6. 6.Step 6: Restore context. Once complete, the saved register states and return address are popped from the stack back into the CPU registers, allowing the original program to resume seamlessly.
    Final Answer: The CPU completes its current FDE cycle, checks interrupt priority, pushes current register contents and the Program Counter onto the stack, points the Program Counter to the ISR start address, executes the ISR, and finally pops the preserved registers from the stack to resume original execution.

    Question: Explain how a computer system handles multiple interrupts of varying priorities arriving concurrently. [4 marks]

    1. 1.Step 1: Identify that interrupts are assigned fixed or dynamic priority levels.
    2. 2.Step 2: Explain that if an interrupt arrives with a lower or equal priority than the currently executing process/ISR, it is placed in an interrupt queue or held pending.
    3. 3.Step 3: Explain that if a higher-priority interrupt arrives while an ISR is already running, the CPU suspends the current ISR, pushes its state onto the stack, and services the new higher-priority interrupt (nested interrupts).
    4. 4.Step 4: Conclude that once the higher-priority ISR finishes, previous ISR states are popped in Last-In, First-Out (LIFO) order.
    Final Answer: Interrupts are evaluated by assigned priority levels; higher-priority interrupts can pre-empt lower-priority routines by pushing current ISR states onto the stack (nested interrupts), whereas lower-priority interrupts remain queued until the processor becomes available.
    Active Recall Memory Test
    At what exact point during the processor cycle does the CPU check for interrupt signals?
    Key Fact: At the very end of the Fetch-Decode-Execute cycle (after the execute phase, before the next fetch phase).
    Which specific data structure is used by the CPU to save the state of interrupted processes?
    Key Fact: The system call stack.
    What routine is executed to service an interrupt, and how does the CPU find its starting address?
    Key Fact: The Interrupt Service Routine (ISR); its starting address is retrieved from the Interrupt Vector Table.
    What happens if an incoming interrupt has a lower priority than the process currently executing?
    Key Fact: It is held pending or placed in an interrupt queue until the higher-priority task completes.
    Frequently Asked Questions
    What is the difference between a hardware interrupt and a software interrupt?
    A hardware interrupt is generated by an external physical device, such as a keyboard press, mouse movement, or printer out-of-paper sensor, sent via dedicated electrical lines. A software interrupt (often called a trap or exception) is generated internally by the CPU when an instruction requires an operating system service or encounters an illegal condition, such as a division by zero or an invalid memory address access.
    Why does the processor push registers to the stack instead of general RAM?
    The processor saves register states to a stack because of its Last-In, First-Out (LIFO) nature. This design is essential for handling nested interrupts, where an interrupt handler itself gets interrupted by a higher-priority event. Using the stack ensures that execution contexts can be restored in the exact reverse order in which they were suspended without overwriting data.
    Does an interrupt stop the CPU from executing instructions?
    No, an interrupt never truly halts the CPU. Instead, it alters which instructions are being executed. The CPU finishes its current instruction, redirects its Program Counter to the instructions inside the Interrupt Service Routine (ISR), executes those, and then returns to the original code sequence.
    What is an Interrupt Vector Table?
    An Interrupt Vector Table (IVT) is an array of memory addresses located in primary storage that points directly to the start of different Interrupt Service Routines (ISRs). When an interrupt signal with a specific identifier is received, the CPU indexes into the IVT to look up the exact memory address of the corresponding handler code.

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