Machine-code/assembly language operations — AQA A-Level Computer Science

Machine code represents the fundamental native instructions executed directly by the central processing unit, consisting entirely of binary bit patterns divided into an opcode and one or more operands. Assembly language provides a human-readable mnemonic representation of this machine code, forming a direct one-to-one correspondence that allows low-level access to processor registers and system memory.

Understanding assembly operations is central to AQA A-Level Computer Science because it bridges high-level procedural abstraction with physical computer architecture. It underpins how compilers generate executable code, how addressing modes determine operand retrieval, and how bit manipulation and status registers control hardware devices.

• →Instruction Structure: Every machine instruction consists of an Operation Code (Opcode), which tells the control unit what operation to execute, and an Operand, which holds data or memory references.
• →Addressing Modes: Immediate addressing ('#value') uses the operand directly as the datum, direct addressing uses the operand as the memory address of the datum, while register addressing uses processor registers.
• →Status Register and Branching: The Compare instruction ('CMP') performs subtraction to update status flags (Zero, Negative, Carry), which conditional branch instructions ('BEQ', 'BNE', 'BGT', 'BLT') evaluate to direct program flow.
• →Bitwise Logical Operations: 'AND', 'ORR', 'EOR', and 'MVN' operate on corresponding individual bits in registers, enabling masking techniques to isolate, set, or invert specific bits.
• →Shift Operations: Logical Shift Left ('LSL') multiplies unsigned integers by powers of two by shifting bits left and inserting zeros, while Logical Shift Right ('LSR') divides by powers of two.

• Identifies the operation type of an instruction from its mnemonic or opcode.
• Identifies the operands and the storage locations they refer to.
• Predicts the effect of an instruction on registers or memory.
• Traces the sequence of execution through a short program correctly.

• 💡Write down the effect of each instruction on registers or memory as you trace the program.
• 💡Check the destination operand to see which storage location is changed.
• 💡Trace execution in order, noting any jump that changes the next instruction.
• 💡Always draw a trace table containing a column for each register and the Status Register condition flags whenever solving loop-based assembly questions.
• 💡When asked to explain the difference between addressing modes, always provide an annotated example showing how the operand field is decoded by the CPU for each mode.
• 💡Ensure you use valid AQA-specific mnemonics from the specification (e.g. 'LDR', 'STR', 'ADD', 'SUB', 'MOV', 'CMP', 'B', 'AND', 'ORR', 'EOR', 'LSL', 'LSR') rather than generic x86 or standard ARM syntax.

• Confuses the operation with its operands; the mnemonic states what is done, the operands state what it is done to.
• Assumes an instruction changes memory when it only changes a register; check the destination carefully.
• Ignores the effect of a jump or branch on the order of execution.
• Believing assembly instructions can access two arbitrary main memory locations simultaneously; in load-store architectures, memory values must first be loaded into registers ('LDR') before arithmetic processing, and then stored back ('STR').
• Confusing Logical Shift Right ('LSR') with Arithmetic Shift Right ('ASR'); LSR always inserts a zero into the most significant bit, whereas ASR preserves the sign bit to maintain correct two's complement negative values.
• Assuming that conditional branch instructions execute the comparison themselves; a conditional branch like 'BNE' only reads the condition flags already stored in the Status Register by a preceding instruction like 'CMP' or 'SUB'.

1. 1Day 1-3: Memorise the standard AQA instruction set mnemonics, distinguishing arithmetic, logical, data transfer, and branch instructions.
2. 2Day 4-6: Practice manual register tracing using past exam trace tables, paying special attention to loop counter decrements and conditional flags.
3. 3Day 7-9: Master bit masking and shifting exercises; write code snippets to extract, set, and toggle individual bits using AND, ORR, and EOR.
4. 4Day 10-12: Write full assembly programs from high-level pseudocode algorithms, incorporating selection constructs ('IF-THEN-ELSE') and iteration ('WHILE', 'FOR').
5. 5Day 13-14: Complete timed past paper questions assessing addressing modes, assembly theory, and machine-code binary instruction layouts.

• 📋Register Trace Tables: Candidates must track values across registers (R0, R1, R2, etc.) through sequential and branching instructions until a HALT instruction is reached.
• 📋Code Conversion / Writing: Candidates must write short snippets of assembly code from a given specification or convert a high-level pseudocode loop into assembly.
• 📋Bitwise Masking Problems: Candidates must supply the correct mask and bitwise operator (AND/ORR/EOR) to isolate or alter specific bit flags.
• 📋Conceptual Questions on Addressing Modes: Candidates are asked to compare immediate, direct, indirect, and indexed addressing modes using diagrams or written definitions.