Structure and function of the processor — OCR A-Level Computer Science

The structure and function of the processor is a foundational topic in computer science that explores how the central processing unit (CPU) executes instructions. The processor is the brain of the computer, responsible for fetching, decoding, and executing instructions stored in memory. Understanding its internal components—such as the control unit (CU), arithmetic logic unit (ALU), registers, and buses—is essential for grasping how software controls hardware. This topic also covers the fetch-execute cycle, pipelining, and the role of the program counter (PC), memory address register (MAR), memory data register (MDR), and accumulator (ACC).

In the OCR A-Level specification, this topic appears in Component 1 (Computer Systems) and is assessed through both multiple-choice and extended-response questions. Mastery of the processor's architecture enables students to analyse performance factors like clock speed, cache size, and core count. It also provides a foundation for understanding more advanced concepts such as parallel processing, RISC vs. CISC architectures, and the impact of the Harvard and von Neumann architectures. Without a solid grasp of the processor's inner workings, students will struggle with later topics like assembly language programming and memory management.

This topic is not just about memorising component names; it requires understanding how data flows between components during instruction execution. For example, the fetch-execute cycle involves the PC sending an address to the MAR, the CU initiating a read from memory to the MDR, and then the instruction being decoded and executed by the ALU or CU. Students should be able to trace this cycle step-by-step and explain how pipelining improves throughput by overlapping fetch, decode, and execute stages. Real-world relevance includes understanding why a 3.0 GHz quad-core processor outperforms a 3.0 GHz single-core processor for multitasking.

• →The fetch-execute cycle: fetch instruction from memory, decode it, then execute it using the ALU or CU.
• →Processor components: CU (controls execution), ALU (performs arithmetic/logic), registers (PC, MAR, MDR, ACC, CIR), and buses (data, address, control).
• →Pipelining: overlapping fetch, decode, and execute stages to improve instruction throughput, though hazards (data, control, structural) can reduce efficiency.
• →Von Neumann vs. Harvard architecture: von Neumann uses a single memory for data and instructions (bottleneck), while Harvard uses separate memories for parallel access.
• →Factors affecting performance: clock speed, number of cores, cache size/levels (L1, L2, L3), and word length.

• Identification and function of ALU, Control Unit, and specific registers (PC, ACC, MAR, MDR, CIR).
• Explanation of the data, address, and control buses and their relationship to assembly language.
• Detailed description of the Fetch-Decode-Execute cycle and its impact on register states.
• Factors influencing CPU performance: clock speed, number of cores, and cache memory.
• Explanation of pipelining as a method to improve processor efficiency.
• Comparison of Von Neumann and Harvard architectures, including contemporary processor designs.

• 💡Use clear, technical terminology when describing register operations during the Fetch-Decode-Execute cycle.
• 💡When discussing performance, always link the factor (e.g., cache size) to the reduction in time spent waiting for data from slower main memory.
• 💡Be prepared to draw or label diagrams of the CPU architecture.
• 💡Ensure you can explain how assembly language instructions map directly to the movement of data between registers and memory.
• 💡When describing the fetch-execute cycle, use precise register names (e.g., MAR, MDR) and explain the role of the control unit. Avoid vague terms like 'the CPU gets the instruction'—instead say 'the address in the PC is copied to the MAR via the address bus.'
• 💡For performance questions, always discuss multiple factors: clock speed, cache, cores, and pipelining. A one-factor answer loses marks. Use comparative phrases like 'a larger cache reduces the need to access slower main memory.'
• 💡In extended-response questions, draw a clear diagram of the processor's internal components and label buses. Then annotate the flow of data during the fetch-execute cycle. This shows the examiner you understand the interconnections.

• Confusing the roles of the Memory Address Register (MAR) and Memory Data Register (MDR).
• Failing to explain how the Control Unit manages the flow of data through the buses.
• Inaccurately describing the impact of increasing clock speed without considering thermal or physical constraints.
• Confusing the purpose of cache memory with main memory (RAM).
• Misunderstanding the difference between Von Neumann and Harvard architectures regarding memory access.
• Misconception: The ALU is responsible for fetching instructions. Correction: The control unit (CU) manages the fetch-execute cycle; the ALU only performs calculations and logical operations.
• Misconception: Increasing clock speed always improves performance. Correction: Clock speed is limited by heat and power; other factors like cache size and pipelining efficiency also matter. A higher clock speed may cause overheating or require more voltage.
• Misconception: The program counter (PC) stores the current instruction being executed. Correction: The PC holds the address of the next instruction to be fetched; the current instruction is stored in the current instruction register (CIR).