Systems architecture — AQA GCSE Computer Science

Systems architecture explores the internal design of the central processing unit (CPU) and how hardware components cooperate to process data. It centres on the Von Neumann model, exploring registers, buses, and the fundamental Fetch-Decode-Execute cycle that underpins every digital computer.

Understanding systems architecture enables students to explain how hardware specifications, including clock speed, cache memory, and multi-core processing, directly affect software performance. This foundational topic links directly to memory, secondary storage, and low-level software operations in AQA GCSE Computer Science Paper 1.

• →Von Neumann Architecture: Uses shared memory for both program instructions and program data, linked to the CPU via address, data, and control buses.
• →CPU Registers: Dedicated high-speed storage locations inside the CPU, including the MAR, MDR, PC, and Accumulator (ACC).
• →The Fetch-Decode-Execute Cycle: The continuous sequential cycle where instructions are retrieved from RAM, interpreted by the CU, and executed by the ALU or registers.
• →CPU Performance Factors: System performance is determined by the interaction between clock speed (Hz), cache capacity/levels (L1, L2, L3), and the number of processor cores.
• →Embedded Systems: Dedicated computers built into larger physical machines designed to perform specific, repetitive control tasks with limited hardware resources.

• Fetch is the first stage of the fetch–decode–execute cycle.
• The next instruction is copied from main memory (RAM) into the CPU.
• The program counter holds the address of the next instruction, which is sent to memory.
• The fetched instruction is placed in the current instruction register (CIR).
• The program counter is incremented to point to the following instruction.
• Fetch does not execute or decode the instruction; those are later stages.

• 💡Link each stage to a register: PC supplies the address, CIR holds the fetched instruction.
• 💡Use the phrase 'next instruction' to show you know fetch looks ahead, not at the current one.
• 💡If asked to order stages, put fetch first, then decode, then execute.
• 💡When naming registers, always use the full formal term alongside the acronym at least once (e.g. 'Memory Data Register (MDR)') to guarantee credit.
• 💡In questions asking about clock speed, explicitly include the unit 'Hertz' and define it as 'cycles per second' rather than 'operations per second'.
• 💡For multi-core comparison questions, explicitly use the term 'parallel processing' and mention the constraint of 'instruction dependencies' to reach top-band marks.

• Confusing fetch with execute: the correction is that fetch only brings the instruction into the CPU; carrying it out is the execute stage.
• Saying the instruction is fetched from the hard disk or cache: the correction is that the next instruction is fetched from main memory.
• Thinking fetch stores a result back to memory: the correction is that fetch reads the instruction in; writing results back is a later step.
• Believing that Cache memory stores long-term files like a hard drive; cache is volatile, extremely fast SRAM located on or next to the CPU to store frequently used instructions and data.
• Thinking that 'clock speed' means how many instructions are completed per second; clock speed measures clock cycles per second, and some instructions take multiple cycles to complete.
• Assuming an embedded system is simply any small computing device like a smartphone; smartphones are general-purpose computers, whereas embedded systems (e.g., washing machine controllers) execute dedicated firmware.

1. 1Step 1: Memorise the Von Neumann diagram, labelling the CU, ALU, registers (PC, MAR, MDR, ACC), and system buses accurately.
2. 2Step 2: Write out the step-by-step Fetch-Decode-Execute cycle using bullet points, ensuring register transfers are clearly stated.
3. 3Step 3: Create comparison flashcards detailing how clock speed, cache size, and core count specifically improve or constrain CPU performance.
4. 4Step 4: Practice distinguishing between general-purpose systems and embedded systems with five concrete real-world examples.
5. 5Step 5: Complete timed past-paper questions focusing on 4-mark and 6-mark explain/evaluate stems from recent AQA Paper 1 papers.

• 📋Register identification questions: Short 1-2 mark questions asking which register holds an address, data, or calculation output during a specific stage.
• 📋Cycle trace explanations: 3-4 mark questions requiring an ordered description of the Fetch, Decode, or Execute stages.
• 📋Performance evaluation scenarios: 4-6 mark extended responses evaluating the effect of upgrading specific CPU components for given user requirements.
• 📋Embedded systems characteristics: 2-3 mark questions requiring students to define an embedded system and identify its operational benefits (e.g., low power, reliability).