Architecture of the CPU — OCR GCSE Computer Science
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Architecture of the CPU explained
Architecture of the CPU covers 3 specification points, including The purpose of the CPU The fetch-execute cycle and Common CPU components and their function ALU….
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The purpose of the CPU The fetch-execute cycle
The CPU is the processor that runs program instructions held in main memory, so its purpose is to fetch each instruction, decode it, carry it out and store any result. The fetch-decode-execute cycle repeats continuously while the computer is on. In the fetch stage the address in the program counter is copied to the memory address register, the instruction at that address is transferred to the memory data register, and the program counter is incremented ready for the next instruction. In the decode stage the control unit works out what the instruction means. In the execute stage the control unit sends control signals; the ALU may calculate, and results are written back to registers or memory. For example, ADD 5 might load a value, add five and store the answer.
Common CPU components and their function ALU (Arithmetic Logic Unit) CU (Control Unit) Cache Registers
The CPU contains components that work together to run instructions. The arithmetic logic unit performs arithmetic such as addition and subtraction and logical operations such as AND, OR and comparisons. The control unit decodes instructions and sends control signals that coordinate the other components and the timing of data movement. Cache is fast memory close to the CPU that stores frequently used instructions and data to reduce slower main memory access. Registers are very small, very fast storage locations inside the CPU, such as the program counter, memory address register, memory data register, current instruction register and accumulator, each holding a current value during processing. For example, during an addition the control unit decodes the instruction, the ALU calculates, and the result may be held in the accumulator.
Von Neumann architecture MAR (Memory Address Register) MDR (Memory Data Register) Program Counter Accumulator
Von Neumann architecture stores both program instructions and data in the same main memory, fetched and executed in a repeating cycle. The Program Counter holds the address of the next instruction; during the fetch stage its value is copied to the MAR, which sends that address along the address bus. The memory returns the instruction or data to the MDR via the data bus. The PC is then incremented so it points to the following instruction. The instruction is decoded and executed, and the Accumulator holds intermediate arithmetic and logic results inside the CPU. For example, adding two numbers may load one value into the Accumulator, add the second, and store the result back to memory. Together these registers coordinate the fetch-decode-execute cycle.
Your focus
- Describe the purpose of the CPU in processing instructions and data.
- Outline the stages of the fetch-decode-execute cycle in the correct order.
- Explain the role of registers and the control unit within the cycle.
Show all 9 objectives
- Identify the common components inside the CPU.
- Describe the function of the ALU, control unit, cache and registers.
- Explain how the components work together when an instruction is processed.
- Identify the Program Counter, MAR, MDR and Accumulator and state what each holds.
- Describe the sequence of events in the fetch-decode-execute cycle using the correct registers, including when the PC is incremented.
- Explain how Von Neumann architecture uses a single memory for instructions and data.
Architecture of the CPU flashcards
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CPU purpose
Architecture of the CPU exam tips
Marking Points
- States that the CPU processes instructions and data by repeatedly carrying out the fetch-decode-execute cycle.
- Describes the fetch stage: the program counter holds the address of the next instruction, which is copied to the memory address register and fetched into the memory data register.
- Explains that the program counter is incremented during the fetch stage so the next instruction is fetched in the following cycle.
- Describes the decode stage: the control unit decodes the instruction to work out what it means.
- Describes the execute stage: the control unit coordinates the components that carry out the instruction.
- Explains that results may be written back to registers or main memory before the cycle repeats.
- States that the ALU carries out arithmetic operations and logical operations or comparisons.
- Explains that the control unit decodes instructions and sends control signals to coordinate the CPU and other components.
- Describes cache as fast memory that holds frequently used instructions and data to reduce access time to main memory.
- Describes registers as small, fast storage locations inside the CPU that hold current instructions, addresses or data during processing.
- Links the components together, for example the control unit directing data between registers while the ALU performs an operation.
- States that Von Neumann architecture uses a single shared main memory for both instructions and data.
- Describes the Program Counter as holding the address of the next instruction to be fetched.
- Explains that the MAR holds the address of the memory location currently being read from or written to.
- Explains that the MDR holds the data or instruction fetched from memory, or the data to be written to memory.
- Describes the Accumulator as a register that stores intermediate results of arithmetic and logic operations.
- Outlines the sequence: PC → MAR → memory → MDR → decode → execute, with the PC incremented during the fetch stage after the address is copied to the MAR.
- Uses correct register names and explains the role of each within the fetch-decode-execute cycle.
Examiner Tips
- 💡Use the technical register names accurately, such as program counter, memory address register and memory data register.
- 💡Link each stage to what happens next, so the sequence reads as a continuous cycle rather than a list of parts.
- 💡When asked about purpose, start with processing instructions and data, then use the cycle as the explanation.
- 💡Keep decode and execute as separate stages in your answer.
- 💡Match each component to its function using the exact terms ALU, control unit, cache and registers.
- 💡Give one clear example for the ALU, such as adding two numbers or testing whether a value is zero.
- 💡When comparing cache and registers, mention both speed and size to show the difference.
- 💡When asked to describe the role of a register, name the register and state exactly what it holds, for example 'the MAR holds the address of the memory location being accessed'.
- 💡For a sequencing question, write the steps in order and include the role of the PC, MAR, MDR and Accumulator where relevant; state that the PC increments during fetch.
- 💡Use the terms 'address', 'data' and 'instruction' precisely; avoid saying 'the MAR holds the data' because that is the MDR's role.
- 💡If a question asks about Von Neumann architecture, mention the shared memory for instructions and data as well as the registers.
Common Mistakes
- Saying the CPU stores all programs permanently; correction: programs are held in main memory or secondary storage, and the CPU only holds current instructions and data in registers and cache.
- Confusing the program counter with the memory address register; correction: the program counter holds the address of the next instruction, while the memory address register holds the address currently being accessed.
- Believing the cycle happens once per program; correction: the fetch-decode-execute cycle repeats for every instruction while the computer runs.
- Combining decode with execute; correction: decode is a separate stage that happens before execute.
- Treating cache as the same as main memory; correction: cache is smaller, faster and closer to the CPU, and it stores copies of frequently used data rather than the whole program.
- Saying the ALU only does arithmetic; correction: it also performs logical operations such as AND, OR and comparisons.
- Describing registers as large storage; correction: registers are very small and very fast, holding only the values needed at that moment.
- Confusing the MAR and MDR: the MAR holds an address, while the MDR holds data or an instruction. Correction: remember MAR = address, MDR = data.
- Thinking the Program Counter holds the instruction itself rather than its address. Correction: the PC holds the address of the next instruction; the instruction is fetched into the MDR.
- Believing the Accumulator stores the address of the next instruction. Correction: the Accumulator stores intermediate arithmetic or logic results, not addresses.
- Describing the fetch-decode-execute cycle in the wrong order, such as decoding before fetching. Correction: fetch the instruction, then decode it, then execute it.
- Placing the Program Counter increment after decode or execute. Correction: the PC is incremented during the fetch stage, after its value has been copied to the MAR, so it points to the next instruction.