Sequential logic (A-level only) — AQA A-Level Physics

Sequential logic is a fundamental topic in digital electronics, forming the basis of memory elements, counters, and state machines. Unlike combinational logic, where outputs depend solely on current inputs, sequential circuits use feedback to store past states, enabling them to 'remember' information. This makes them essential in devices such as registers, timers, and computer memory.

In the AQA A-Level Physics specification, you are expected to understand the operation of SR latches, D-type and JK flip-flops, and simple counters. You must be able to analyse timing diagrams, construct state tables, and design basic synchronous and asynchronous circuits. This topic bridges the gap between simple logic gates and complex microprocessor systems, providing a foundation for further study in electronics and computer architecture.

• →Feedback is the key mechanism that distinguishes sequential logic from combinational logic; cross-coupled gates create a bistable memory element.
• →The SR latch has set, reset, hold, and invalid states; the invalid state occurs when both S and R are HIGH simultaneously in a NOR-based latch.
• →Edge-triggered flip-flops (D-type, JK) change state only on a clock edge (rising or falling), while level-triggered latches are transparent when enabled.
• →Counters can be asynchronous (ripple) or synchronous; asynchronous counters suffer from propagation delay, causing temporary incorrect states.
• →State tables and state diagrams are used to design and analyse sequential circuits, showing the next state for each combination of present state and inputs.

• States that a binary counter with n flip-flops has 2ⁿ distinct output states and a modulus of 2ⁿ.
• Describes a BCD counter as one that counts from 0000 to 1001 and then returns to 0000, giving a modulus of 10.
• Explains that a Johnson counter feeds the inverse of the last flip-flop output back to the first input, producing 2n states for n flip-flops.
• Constructs or completes a next-state table showing the output after each clock pulse for a given counting circuit.
• Identifies the modulus of a counter from its sequence or from the number of flip-flops and circuit type.
• Distinguishes between free-running binary counting and truncated sequences such as BCD or Johnson counting.
• Identifies the clock as the input that synchronises state changes and states that the active edge triggers each transition.
• Explains that the reset input clears the counter outputs to zero, either immediately or on the next active clock edge depending on the design.
• Describes the up/down input as selecting whether the counter increments or decrements on each clock pulse.
• Traces the effect of each control input on the next-state table or output sequence of a given circuit.
• Explains the priority of reset over normal counting when both reset and clock signals are present.
• Identify each output node in the circuit and state whether it is taken from a flip-flop (Q or Q̄) or from a combinational gate.
• Track the state of every storage element after each active clock edge before evaluating downstream gates.
• Evaluate combinational gates using the current stored states and any external inputs, applying the correct truth table for each gate.
• Present outputs as a timing diagram or state table with clearly labelled clock pulses and output levels.
• Recognise that while flip-flop states change only at active clock edges, combinational outputs may change asynchronously if external inputs vary between clock pulses.
• Check that unused or asynchronous inputs are held at defined logic levels so outputs are not indeterminate.
• State the number of distinct states n and the binary value of the first unwanted state, which is n itself.
• Select the counter outputs that are high in that unwanted state and combine them with a logic gate to produce the reset signal.
• Connect the decoded signal to the reset pin so the counter clears to zero when the unwanted state is reached.
• Describe the repeating sequence of states from 0 to n − 1 and back to 0.
• Explain that the reset is usually asynchronous, so the counter may clear before the next clock edge.
• Check that the decoding gate produces a high output only for the unwanted state and not for any valid state.
• State the output of each basic gate (NOT, AND, OR, NAND, NOR, XOR) for all input combinations.
• Construct and complete truth tables for circuits containing several gates.
• Derive or interpret a Boolean expression from a gate network.
• Combine gates as building blocks to realise a required logic function.
• Analyse sequential circuits by treating each gate as a block with defined behaviour.

• 💡Draw the full state sequence before answering, then count the states to confirm the modulus.
• 💡For BCD questions, explicitly state the reset condition, for example that 1010 is detected and forces the counter back to 0000.
• 💡When comparing counters, tabulate the number of flip-flops, number of states and feedback arrangement side by side.
• 💡Label the clock, reset and up/down inputs clearly on any circuit diagram before tracing the sequence.
• 💡State the active edge, for example rising or falling, whenever you describe when the count changes.
• 💡Use a short timing diagram or state table to show how reset and up/down alter the sequence, rather than describing it only in words.
• 💡Draw a timing diagram with one row per signal and align all transitions to clock edges or asynchronous input changes.
• 💡Label each clock pulse number so your sequence is easy to follow and check.
• 💡State the logic level of each output at each step rather than describing it vaguely.
• 💡Write the binary value of n before choosing which outputs to decode.
• 💡State clearly which outputs feed the gate and what the gate output does.
• 💡Describe the full repeating sequence so the modulo behaviour is unambiguous.
• 💡Mention that the reset is asynchronous if the circuit uses an asynchronous reset pin.
• 💡Write a truth table with every input combination before deducing any output.
• 💡Label intermediate nodes in a multi-gate circuit so each gate's output is tracked clearly.
• 💡Check the final output against the Boolean expression you have written to confirm consistency.
• 💡Always draw timing diagrams with clearly labelled clock edges and show the propagation delay if asked about asynchronous circuits. Marks are awarded for correct relative timing, not just final values.
• 💡When describing a sequential circuit, explicitly state the type of triggering (edge or level) and the clock input. Use correct terminology such as 'set', 'reset', 'toggle', and 'hold'.
• 💡For design questions, show your working using a state table and excitation table. Even if the final circuit is not perfect, you can gain method marks for correct intermediate steps.

• Assuming a BCD counter has a modulus of 16 because it uses four flip-flops; the correct modulus is 10 because it is truncated at 1001.
• Confusing a Johnson counter with a ring counter; a ring counter recirculates a single 1 and has n states, whereas a Johnson counter inverts the feedback and has 2n states.
• Forgetting that the count advances on the active clock edge, so the output listed for a state is the value after that edge, not before it.
• Treating the clock as a level-sensitive input rather than an edge-triggered one; the correction is that state changes occur only on the specified active edge.
• Assuming reset always acts immediately; the correction is that some counters reset synchronously on the next clock edge, so the design must be checked.
• Believing that up/down changes the clock frequency; the correction is that it changes the direction of the count sequence, not the timing.
• Treating a flip-flop output as changing immediately with its input; the correction is that Q changes only on the active clock edge.
• Evaluating gates before updating the flip-flop states; the correction is to update storage elements first, then evaluate combinational logic.
• Assuming all circuit outputs are strictly synchronous; the correction is to check if combinational gates are connected to external inputs that can change between clock edges.
• Leaving unused inputs floating; the correction is to tie them to a defined logic level so the output is predictable.
• Decoding the state n − 1 instead of n; the correction is to reset on the first state that must not appear, which is n.
• Using an AND gate when the required outputs are not all high; the correction is to choose the gate that matches the polarity of the outputs being decoded.
• Forgetting that the reset clears the counter to zero rather than to one; the correction is to state the reset state explicitly.
• Assuming the decoded state is stable for a full clock period; the correction is to note that asynchronous reset may clear the counter almost immediately.
• Attempting to explain gate operation using internal transistor arrangements; the correction is to describe only the input-output relationship of the gate.
• Confusing NAND with AND or NOR with OR; the correction is to remember that NAND and NOR are the inverted forms of AND and OR respectively.
• Assuming a gate output depends on past inputs; the correction is to treat combinational gates as responding only to their present inputs.
• Students often think that a latch and a flip-flop are the same thing. In reality, a latch is level-triggered and transparent when enabled, while a flip-flop is edge-triggered and only changes on a clock edge.
• Many believe that the invalid state in an SR latch is harmless. In fact, if both S and R are HIGH and then both go LOW, the output state is unpredictable and may oscillate, so this condition must be avoided in design.
• Students frequently assume that asynchronous counters count in perfect binary order with no glitches. Due to propagation delays, intermediate states can appear, which may cause errors in connected circuitry.

1. 1Day 1-2: Revise logic gates and combinational logic. Ensure you can write truth tables and Boolean expressions confidently.
2. 2Day 3-4: Study the SR latch in detail. Draw the circuit, derive its truth table, and practise timing diagrams for various input sequences.
3. 3Day 5-6: Learn about D-type and JK flip-flops. Compare edge-triggered and level-triggered behaviour. Practice drawing output waveforms for given clock and input signals.
4. 4Day 7-8: Explore counters. Build a 2-bit and 3-bit asynchronous counter, then a synchronous counter. Draw state tables and timing diagrams.
5. 5Day 9-10: Attempt past paper questions on sequential logic. Focus on design and analysis questions. Review mark schemes to understand the level of detail required.

• 📋Timing diagram analysis: Given a circuit and input waveforms, sketch the output waveform. Advice: carefully track each gate's output, remember feedback, and label propagation delays if asynchronous.
• 📋Circuit design: Design a sequential circuit (e.g., a modulo-5 counter) using flip-flops. Advice: start with a state table, derive excitation inputs, and draw the final circuit clearly.
• 📋Explanation of operation: Describe how a given sequential circuit works, including its states and transitions. Advice: use correct terminology and refer to the clock and feedback paths.
• 📋Comparison question: Compare synchronous and asynchronous counters, or latches and flip-flops. Advice: structure your answer in a table or bullet points, highlighting differences in triggering, speed, and application.